1. Field of the Invention
The invention relates to a level shifter circuit, and more particularly to a level shifter circuit capable of receiving high frequency and low voltage input signals.
2. Description of the Related Art
A level shifter circuit is generally configured to convert signals between two different voltage levels. For example, the level shifter is used to convert the low voltage of an input signal to a higher voltage that may be preferably used for the circuit with higher operating voltage.
FIG. 1 shows a circuit diagram of conventional digital level shifter 10. The conventional level shifter 10 consists of two NMOS transistors 103A and 103B, two PMOS transistors 104A and 104B, and three inverters 101, 102A and 102B, wherein the voltage level of the input signal SIN is lower than that of the voltage supplier VDD. When the input signal SIN is a high voltage signal to turn on the NMOS transistor 103A, the voltage at node X is pulled down to VSS due to the turned on NMOS transistor 103A. The low voltage VSS at node X further turns on the PMOS transistor 104B and the voltage at node Y is pulled high to VDD. After buffered by inverters 102A and 102B, the voltage of output signal SOUT is pulled high to VDD. Contrarily, when the input signal SIN is a low voltage signal that is unable to turn on the NMOS transistor 103A, the low voltage signal will be inverted by the inverter 101 to become a high voltage signal capable of turning on the NMOS transistor 103B, and the voltage at node Y is then pulled down to VSS due to the turned on NMOS transistor 103B. After buffered by inverters 102A and 102B, the voltage of output signal SOUT is pulled down to VSS.
However, when the input signal SIN is a high frequency and low voltage signal, the low voltage causes the current flowing through the NMOS transistor 103A to be small when the NMOS transistor 103A is turned on. Thus, it takes more time to pull the node X down to VSS, and causes the response time of the level shifter to increase. For example, when the input signal SIN is a 5 MHz Master Clock (MCK) signal, since the response time at node X exceeds 200 ns, it is not fast enough to respond to the voltage variation of the MCK signal and the voltage level of the output signal SOUT is unable to be accordingly changed. Thus, the level shifting function fails. If the conducting current of the NMOS transistor 103A is increased by enlarging the width of the NMOS transistor so as to increase the response speed of the high frequency and low voltage input signal, the circuit area of the level shifter 10 will become too large and not be suitable for mass usage.
Thus, a novel level shifter circuit capable of receiving high frequency and low voltage input signals is highly desired.